Recently, researches have been carried out on insulated-gate semiconductor devices comprising active layers (also known as active regions) in the form of thin films on an insulating substrate. Especially, thin-film insulated-gate transistors, or so-called thin-film transistors (TFTS) have been earnestly investigated. These devices are intended to be used to control pixels on a display device having a matrix structure such as a liquid-crystal display. They are classified into amorphous silicon TFTs or polysilicon TFTs according to the used semiconductor material and the state of the crystal. Also, researches have recently been made on materials showing a condition intermediate between polysilicon and amorphous state. These materials are called semi-amorphous materials and considered as an amorphous structure in which crystallites are floating. This kind of material is an excellent one combining both high mobility of a single-crystal condition and low leakage current of an amorphous state, as described later.
Furthermore, polysilicon TFTs are used on an integrated circuit of single-crystal silicon. This is known as SOI (silicon-on-insulator) technique. For example, these TFTs are used as load transistors in an SRAM of large scale integration. In this case, however, amorphous silicon TFTs are quite rarely employed.
A semiconductor circuit on an insulating substrate can operate at a quite high speed because conductive interconnects are not capacitance-coupled to the substrate. A proposal has been made to use semiconductor circuits of this kind as ultrahigh-speed microprocessors and ultrahigh-speed memories.
Generally, amorphous semiconductors have low field mobilities and thus cannot be used in those TFTs which are required to operate at high speeds. Also, P-type amorphous silicon has an extremely low field mobility and so it is impossible to fabricate P-channel TFTs, or PMOS TFTs. Therefore, it is impossible to fabricate complementary MOS (CMOS) circuits by combining P-channel TFTs, or PMOS TFTs, and N-channel TFTs, or NMOS TFTs.
However, TFTs fabricated from an amorphous semiconductor have the advantage that they have low OFF current. Hence, these TFTs are used in applications where very high speed operation is not required, only one conductivity type suffices, and electric charge must be held well, such as active-matrix transistors of a liquid-crystal device.
On the other hand, polycrystalline semiconductors have larger field mobilities than amorphous semiconductors and hence are capable of high-speed operation. For example, TFTs using a silicon film recrystallized by laser annealing show a field mobility as high as 300 cm2/V·s, which is very much large like field mobility of about 500 cm2/V·s of MOS transistors formed on a normal single-crystal silicon substrate. The operating speed of a MOS circuit on a single crystal of silicon is limited by the parasitic capacitance between the substrate and the conductive interconnects. In contrast, in case of the polycrystalline semiconductors (the recrystallized silicon film), such restrictions do not exist because the circuit lies on an insulating substrate. Consequently, an extremely high-speed operation is expected.
PMOS TFTs can be fabricated from polysilicon similarly to NMOS TFTS. Therefore, CMOS circuits can be formed. For example, active-matrix liquid-crystal displays having a so-called monolithic structure, i.e., not only the active-matrix portions but also peripheral portions such as drivers are fabricated from CMOS polycrystalline TFTs, are known.
TFTs used in the aforementioned SRAMs are formed, taking account of this point. PMOS devices are fabricated from TFTs and used as load transistors.
In normal amorphous TFTs, it is difficult to form source/drain regions by a self-aligning process as used in single-crystal IC fabrication techniques. Parasitic capacitance due to geometrical overlap of the gate electrodes and the source/drain regions presents problems. In contrast, polycrystalline TFTs can make use of a self-aligning process and, therefore, parasitic capacitance can be suppressed greatly.
Although polysilicon TFTs have features described above, some problems have been pointed out. In a general polysilicon TFT, an active layer is formed on an insulating substrate. A gate-insulating film and gate electrodes are formed on the active layer. This structure is known as the coplanar type. Though this structure can utilize a self-aligning process, it is difficult to reduce the leakage current (OFF current) from the active layer.
The causes of this leakage current are not fully understood but a major cause is due to interface-trapped charges created between the underlying base and the active layer. Accordingly, the problems of the leakage current are solved by fabricating the interface with meticulous care and reducing the interface trap density to such an extent that it is almost equal to the density at the interface between the gate-oxide film and the active layer.
In particular, in a high-temperature process (the highest process temperature is on the order of 1000° C.), a substrate is fabricated from quartz. A coating of silicon is formed on the substrate and thermally oxidized at about 1000° C. to form a clean surface. Then, an active silicon layer is formed by low-pressure CVD or other method.
In a low-temperature process (the highest process temperature is lower than 650° C.; also known as an intermediate-temperature process), a silicon oxide film having an interface trap density as low as that of the gate-insulated film is formed as a base film between the substrate and the active layer. Sputtering is an excellent method of forming the silicon oxide film. Oxide films having excellent characteristics can also be derived by ECR CVD or plasma-assisted CVD of TEOS.
However, it has been still impossible to reduce the leakage current. Especially, the leakage current from the NMOS was greater than that of the PMOS by one order of magnitude or more. We have conjectured that weak N-type of the active layer causes this great leakage current. In practice, we have observed with high reproducibility that the threshold voltages of PMOS and NMOS devices manufactured by high-temperature and low-temperature processes shift in the negative direction. Especially, in the case of high-purity silicon not doped with any other dopant, we have also inferred that the active layer becomes a weak N type in case of poor crystallinity being obtained as in the case of amorphous silicon. Polycrystalline silicon fabricated by a high-temperature process contains numerous lattice defects and dangling bonds unlike a perfect single crystal of silicon. These become donors and supply electrons. Of course, the possibility of the effect of a trace amount of impurity elements such as sodium remains.
In any case, if any one of the above-described causes exists, then we can explain away the above phenomena, i.e. NMOS devices have much lower threshold voltages and a larger amount of leakage current than PMOS devices. This is illustrated in FIGS. 1, (A)-(B). As shown in FIG. 1(A), the N+ source 12 of an NMOS is grounded. A positive voltage is applied to the N+ drain 13. Under this condition, if a voltage higher than the threshold voltage Vth of a gate electrode 11 is applied to it, then a channel is formed on the side of the gate electrode of an active layer 14, and a drain current flows as indicated by the arrow of the solid line. However, since the active layer 14 is of a weak N-type (N−-type), an electrical current which hardly depends on the gate voltage flows from the source to the drain as indicated by the arrow of broken lines.
Even if the potential at the gate electrode is lower than the threshold voltage Vth, then the current indicated by the arrow of broken lines keeps flowing. If the potential at the gate electrode assumes a large negative value, a P-type inversion layer 16 is created, as shown in FIG. 1(B), but the channel is not entirely inverted. Conversely, if an excessive voltage is applied, electrons are accumulated on the opposite side of the gate, thus producing a channel. Data actually obtained about NMOS devices is not inconsistent with the above consideration.
In the case of the PMOS, the threshold voltage is higher because the active layer is of N−-type but the leakage on the opposite side of the gate is reduced greatly. FIGS. 2, (A) and (B), show cases in which a voltage lower than the threshold voltage and a voltage exceeding the threshold voltage are respectively applied to the PMOS.
Such conspicuous leakage current from the NMOS is an impediment in various applications, especially in applications where dynamic operation is needed. For example, in active-matrix arrays of liquid crystals or DRAMs, image information or stored information is lost. Accordingly, it has been necessary to reduce such leakage current.
One method is to make the active layer of the NMOS intrinsic (I-type) or weak P-type. For instance, when the active layer is formed, an appropriate amount of P-type dopant such as boron is implanted only into the NMOS or into both NMOS and PMOS to make the active layer of the NMOS I-type or weak P-type. Then, the threshold voltage of the NMOS should increase, and the leakage current should decrease greatly. However, this method involves some problems.
Usually, a CMOS circuit comprising a substrate on which both NMOS devices and PMOS devices are fabricated is used. Where a dopant should be implanted only into the N-type, excess photolithography steps are needed. Where a P-type dopant should be implanted into the active layers of both NMOS and PMOS devices, subtle dopant implantation techniques are necessitated. If the dosage is too great, the threshold voltage of the PMOS decreases, and the leakage current increases.
Ion-implantation techniques also pose problems. In implantation techniques where mass separation is effected, it is possible to implant only a requisite dopant element. However, the processed area is small. A so-called ion doping method provides a large processed area but unwanted ions are also implanted, because the method involves no mass-separation step. Consequently, there is a possibility that the dose is not accurate.
In this method of accelerating and implanting ions, localized traps are created at the interface between the active layer and the underlying base. Unlike the prior art ion implantation into a single crystal of semiconductor, the implantation is done over an insulating substrate and so conspicuous charge-up takes place. This makes it difficult to accurately control the dosage.
Accordingly, previous introduction of a P-type dopant at the time of the formation of the active layer may be contemplated, but it is difficult to control a trace amount of dopant. Where both NMOS and PMOS are fabricated from the same film, the leakage current from the PMOS will be increased unless the amount is adequate. Where they are fabricated from different films, an additional masking step is required. If the threshold voltage is controlled by this method, the TFTs are made nonuniform in threshold value due to the gas flow and other factors. The threshold value varies greatly from lot to lot.